A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using local interconnects.
The local interconnect is typically a relatively low resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or a trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the density of the circuits increases there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
A problem arises in the formation of a local interconnect due to the relatively poor etch selectivity of the oxide dielectric material to the etch stop layer typically used to prevent overetching into a diffusion region. The overetching may lead to disconnection of the diffusion region at a field edge and result in a poor interconnection. This may best be understood by reference to FIGS. 1-3 to illustrate the concern.
FIG. 1 depicts a cross-section of a semiconductor device arrangement during one step of a local interconnect formation process. A silicon substrate 10 has polycrystalline silicon (hereafter polysilicon) gates 12 and 14 formed thereon. The polysilicon gate 14 is actually formed on the field oxide 16. A spacer 15 (such as an oxide spacer) provides a shielding of the substrate 10 directly under the spacer 15 during implantation or diffusion of dopant substrate 10.
A plurality of silicide regions 18 are formed through conventional silicide techniques, for example, in a self-aligned silicide ("salicide") technique. The material comprising the silicide regions 18 may be selected from different materials, such as titanium silicide, cobalt silicide, tungsten silicide, etc. Silicide regions 18 provide a low resistance contact for the semiconductor devices.
The doped active region 20 is provided in the substrate 10 as defined by the doping. Typically, a heating step is performed to activate the dopants following the introduction of the dopants into the substrate 10.
An etch stop layer 22 is conformally deposited over the semiconductor wafer. An exemplary material for the etch stop layer is silicon oxynitride (SiON) and a conventional method of deposition is plasma enhanced chemical vapor deposition (PECVD). A layer of dielectric material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS), is deposited over the etch stop layer 22 and planarized. The dielectric layer 24 is then covered with a photoresist mask 26 which is patterned and developed with the desired local interconnect opening that is to be etched in the dielectric layer 24. In this example of FIG. 1, the opening in the photoresist layer 26 is positioned to provide a local interconnect opening in the dielectric layer 24 that will eventually connect the gate 14 of one device with the active region 20 of another device.
An etching step is then performed that etches through the dielectric layer 24 in accordance with the pattern in the photoresist layer 26. It is desirable to stop this first etching step at the etch stop layer 22. However, as depicted in FIG. 2, it is often difficult to precisely stop the etch at the etch stop layer 22, especially at the edge of the field 16. In this circumstance, the local interconnect opening 28 undesirably extends into the substrate 10 at area 30. The unintended etching through the etch stop layer 22 allows the etchant to etch the silicide region 18 and the diffusion region 20, creating the dip 30 into the substrate 10.
As seen in FIG. 3, after the deposition of a liner (or "barrier layer") that prevents diffusion of the conductive material into the other areas of the device, the local interconnect opening 28 is filled with a conductive material, such as tungsten 34. However, there remains a disconnection of the diffusion region 20 at the edge of the field 16, caused by the overetching through the etch-stop layer 22 during the etching of the dielectric layer 24. This disconnection and the reduced contact of the conductive metal 34 to the suicide region 18 of the diffusion region 20 decreases the performance of the circuit, and in extreme circumstances, may cause circuit failure.
There is a need for an improved etch selectivity to prevent the weakness at the field edge and disconnection of the diffusion region during a local interconnect formation process.